DDR Memory Termination Regulators, Texas InstrumentsDesigned specifically for bus termination in DDR and QDR memory applications. These sink/source tracking termination regulators are aimed for space saving, low-cost applications with low external part counts.The Texas Instruments TPS51200 device is a sink and source double data rate (DDR)termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration. It maintains a fast transient response and requires a minimum output capacitance of only 20 μF. It supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L,Low-Power DDR3 and DDR4 VTT bus termination.Input Voltage: Supports 2.5-V Rail and 3.3-V RailVLDOIN Voltage Range: 1.1 V to 3.5 VSink and Source Termination Regulator Includes Droop CompensationRequires Minimum Output Capacitance of 20-μF (Typically 3 ´ 10-μF MLCCs) for Memory Termination Applications (DDR)PGOOD to Monitor Output RegulationEN InputREFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor DividerRemote Sensing (VOSNS)±10-mA Buffered Reference (REFOUT)Built-in Soft Start, UVLO, and OCLThermal ShutdownSupports DDR, DDR2, DDR3, DDR3L, Low-Power DDR3, and DDR4 VTT Applications10-Pin VSON Package With Thermal PadDDR Memory Power Solutions, Texas Instruments