10 pcs : A3R1GE30JBF-8E - DRAM DDR2 1Gb, 128Mx8, 800 a.CL5, 1.8V, FBGA-60

DDR2 SDRAM Zentel DDR2 SDRAM features a double-data-rate architecture with two data transfers per clock cycle. The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture. A bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver. DQS is edge-aligned with data for READs, center-aligned with data for WRITEs Differential clock inputs (CK and /CK). The DLL aligns DQ and DQS transitions with CK transitions.